We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS

LSR (Super FX): Difference between revisions

From SnesLab
Jump to: navigation, search
(linkify B)
(→‎See Also: fixed ROL link)
 
(16 intermediate revisions by the same user not shown)
Line 1: Line 1:
{| class="wikitable" style="float:right;clear:right;width:40%"
{| class="wikitable" style="float:right;clear:right;width:50%"
!colspan="8"|Basic Info
!colspan="8"|Basic Info
|+
|+
|'''Addressing Mode'''
|'''Opcode'''
|'''Opcode'''
|'''Length'''
|'''Length'''
Line 8: Line 9:
|'''Cache Speed'''
|'''Cache Speed'''
|+
|+
|[[Implied]] (type 1)
|03
|03
|1 byte
|1 byte
Line 22: Line 24:
|[[ALT2]]
|[[ALT2]]
|[[O/V]]
|[[O/V]]
|S
|[[Sign Flag|S]]
|[[CY]]
|[[CY]]
|Z
|[[Zero Flag|Z]]
|+
|+
|0
|0
Line 31: Line 33:
|.
|.
|0
|0
|
|CY
|
|Z
|}
|}


'''LSR''' (Logical Shift Right) is a [[Super FX]] instruction that shifts all bits of the [[source register]]'s value to the right one bit while shifting a zero into the most significant bit, storing the result in the [[destination register]].  Bit 0 is shifted into [[CY]].  The source register itself is left unchanged.
'''LSR''' (Logical Shift Right) is a [[Super FX]] instruction that shifts all bits of the [[source register]]'s value to the right one bit while shifting a zero into the most significant bit, storing the result in the [[destination register]].  Bit 0 is shifted into [[CY]].  The source register itself is left unchanged.
The [[ALT0]] state is restored.
The source and destination registers should be specified in advance using [[WITH]], [[FROM]], or [[TO]].  Otherwise, R<sub>0</sub> serves as the default.
==== Syntax ====
<pre>
LSR
</pre>
==== Example ====
Let:
S<sub>reg</sub> : R<sub>8</sub>
D<sub>reg</sub> : R<sub>0</sub>
R<sub>8</sub> = b53fh (1011 0101 0011 1111b)
After executing LSR:
R<sub>0</sub> = 5a9fh (0101 1010 1001 1111b)
CY = 1


[[File:gsu_lsr.png]]
[[File:gsu_lsr.png]]
Line 43: Line 63:
* [[DIV2]]
* [[DIV2]]
* [[LSR]]
* [[LSR]]
* [[LSR (SPC700)]]
* [[ROR (Super FX)]]
* [[ROL (Super FX)]]
* [[ROR]]


=== External Links ===
=== External Links ===
* Official Nintendo documentation on LSR: [https://archive.org/details/SNESDevManual/book2/page/n234 Page 2-9-78 of Book II]
* Official Nintendo documentation on LSR: 9.55 on [https://archive.org/details/SNESDevManual/book2/page/n234 page 2-9-78 of Book II]


[[Category:ASM]]
[[Category:ASM]]
Line 51: Line 75:
[[Category:Shift Instructions]]
[[Category:Shift Instructions]]
[[Category:One-byte Instructions]]
[[Category:One-byte Instructions]]
[[Category:Expects Sreg/Dreg Prearranged]]

Latest revision as of 02:01, 22 August 2024

Basic Info
Addressing Mode Opcode Length ROM Speed RAM Speed Cache Speed
Implied (type 1) 03 1 byte 3 cycles 3 cycles 1 cycle
Flags Affected
B ALT1 ALT2 O/V S CY Z
0 0 0 . 0 CY Z

LSR (Logical Shift Right) is a Super FX instruction that shifts all bits of the source register's value to the right one bit while shifting a zero into the most significant bit, storing the result in the destination register. Bit 0 is shifted into CY. The source register itself is left unchanged.

The ALT0 state is restored.

The source and destination registers should be specified in advance using WITH, FROM, or TO. Otherwise, R0 serves as the default.

Syntax

LSR

Example

Let:

Sreg : R8
Dreg : R0
R8 = b53fh (1011 0101 0011 1111b)

After executing LSR:

R0 = 5a9fh (0101 1010 1001 1111b)
CY = 1

gsu lsr.png

See Also

External Links