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OR (Super FX): Difference between revisions
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!colspan="8"|Basic Info | !colspan="8"|Basic Info | ||
|+ | |+ | ||
|'''Addressing Mode''' | |||
|'''Opcode''' | |'''Opcode''' | ||
|'''Length''' | |'''Length''' | ||
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|'''Cache Speed''' | |'''Cache Speed''' | ||
|+ | |+ | ||
|[[Immediate]] | |||
|3ECn | |||
|2 bytes | |||
|6 cycles | |||
|6 cycles | |||
|2 cycle | |||
|+ | |||
|[[Implied]] (type 1) | |||
|Cn | |Cn | ||
|1 byte | |1 byte | ||
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|[[Sign Flag|S]] | |[[Sign Flag|S]] | ||
|[[CY]] | |[[CY]] | ||
|Z | |[[Zero Flag|Z]] | ||
|+ | |+ | ||
|0 | |0 | ||
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|0 | |0 | ||
|. | |. | ||
| | |S | ||
|. | |. | ||
| | |Z | ||
|} | |} | ||
'''OR''' is a [[Super FX]] instruction that performs a logical bitwise OR between the [[source register]] and its operand. The disjunction is stored in the [[destination register]]. The operand may be any register from R<sub>1</sub> to R<sub>15</sub> or any immediate value from 1 to 15. | '''OR''' is a [[Super FX]] instruction that performs a logical bitwise OR between the [[source register]] and its operand. The disjunction is stored in the [[destination register]]. The operand may be any register from R<sub>1</sub> to R<sub>15</sub> or any immediate value from 1 to 15. | ||
The [[ALT0]] state is restored. | |||
The source and destination registers should be specified in advance using [[WITH]], [[FROM]], or [[TO]]. Otherwise, R<sub>0</sub> serves as the default. | |||
==== Syntax ==== | |||
<pre> | |||
OR Rn | |||
OR #n | |||
</pre> | |||
==== Example 1 ==== | |||
Let: | |||
S<sub>reg</sub> : R<sub>4</sub> | |||
D<sub>reg</sub> : R<sub>5</sub> | |||
R<sub>4</sub> = 6368h (0110 0011 0110 1000b) | |||
R<sub>2</sub> = 168ch (0001 0110 1000 1100b) | |||
After executing OR R<sub>2</sub>: | |||
R<sub>5</sub> = 77ech (0111 0111 1110 1100b) | |||
==== Example 2 ==== | |||
Let: | |||
S<sub>reg</sub> : R<sub>7</sub> | |||
D<sub>reg</sub> : R<sub>5</sub> | |||
R<sub>7</sub> = 5fa2h (0101 1111 1010 0010b) | |||
After executing OR #5h: | |||
R<sub>5</sub> = 5fa7h (0101 1111 1010 0111b) | |||
=== See Also === | === See Also === | ||
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* [[XOR (Super FX)]] | * [[XOR (Super FX)]] | ||
* [[ORA]] | * [[ORA]] | ||
* [[EOR]] | |||
* [[ALT2]] | |||
* [[OR (SPC700)]] | |||
=== External Links === | === External Links === | ||
* Official Nintendo documentation on OR: 9.70 on [https://archive.org/details/SNESDevManual/book2/page/n253 page 2-9-97 of Book II] | * Official Nintendo documentation on OR: 9.70 on [https://archive.org/details/SNESDevManual/book2/page/n253 page 2-9-97 of Book II] | ||
* example: [https://archive.org/details/SNESDevManual/book2/page/n254 page 2-9-98 of Book II], lbid. | * example 1: [https://archive.org/details/SNESDevManual/book2/page/n254 page 2-9-98 of Book II], lbid. | ||
* immediate OR: 9.71 on [https://archive.org/details/SNESDevManual/book2/page/n255 page 2-9-99 of Book II] | |||
[[Category:ASM]] | [[Category:ASM]] | ||
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[[Category:Logical Operation Instructions]] | [[Category:Logical Operation Instructions]] | ||
[[Category:One-byte Instructions]] | [[Category:One-byte Instructions]] | ||
[[Category:Expects Sreg/Dreg Prearranged]] | |||
Latest revision as of 19:20, 30 July 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | ROM Speed | RAM Speed | Cache Speed | ||
| Immediate | 3ECn | 2 bytes | 6 cycles | 6 cycles | 2 cycle | ||
| Implied (type 1) | Cn | 1 byte | 3 cycles | 3 cycles | 1 cycle | ||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | . | S | . | Z | ||
OR is a Super FX instruction that performs a logical bitwise OR between the source register and its operand. The disjunction is stored in the destination register. The operand may be any register from R1 to R15 or any immediate value from 1 to 15.
The ALT0 state is restored.
The source and destination registers should be specified in advance using WITH, FROM, or TO. Otherwise, R0 serves as the default.
Syntax
OR Rn OR #n
Example 1
Let:
Sreg : R4 Dreg : R5 R4 = 6368h (0110 0011 0110 1000b) R2 = 168ch (0001 0110 1000 1100b)
After executing OR R2:
R5 = 77ech (0111 0111 1110 1100b)
Example 2
Let:
Sreg : R7 Dreg : R5 R7 = 5fa2h (0101 1111 1010 0010b)
After executing OR #5h:
R5 = 5fa7h (0101 1111 1010 0111b)
See Also
External Links
- Official Nintendo documentation on OR: 9.70 on page 2-9-97 of Book II
- example 1: page 2-9-98 of Book II, lbid.
- immediate OR: 9.71 on page 2-9-99 of Book II