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STB (Super FX): Difference between revisions
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|'''Cache Speed''' | |'''Cache Speed''' | ||
|+ | |+ | ||
| | |[[Implied Indirect]] | ||
|3D3m | |3D3m | ||
|2 bytes | |2 bytes | ||
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|[[Sign Flag|S]] | |[[Sign Flag|S]] | ||
|[[CY]] | |[[CY]] | ||
|Z | |[[Zero Flag|Z]] | ||
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|0 | |0 | ||
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'''STB''' (Store Byte) is a [[Super FX]] instruction that stores | '''STB''' (Store Byte) is a [[Super FX]] instruction that stores the low byte of the [[source register]] to the [[Game Pak]]. STB expects the target address to be in the R<sub>m</sub> register. The bank must be specified with [[RAMB]]. | ||
The operand may be any register from R<sub>0</sub> to R<sub>11</sub>. The number of cycles can vary because of the [[RAM buffer]]. | |||
The source register should be specified in advance using [[WITH]] or [[FROM]]. Otherwise, R<sub>0</sub> serves as the default. | |||
The [[ALT0]] state is restored. | |||
==== Syntax ==== | |||
<pre> | |||
STB (Rm) | |||
</pre> | |||
==== Example ==== | |||
Let: | |||
S<sub>reg</sub> : R<sub>5</sub> | |||
R<sub>5</sub> = 216ch | |||
R<sub>8</sub> = 9a34h | |||
RAMBR = 70h | |||
After STB (R<sub>8</sub>) is executed: | |||
(70:9A34h) = 6ch | |||
=== See Also === | === See Also === | ||
* [[STW]] | * [[STW]] | ||
* [[LDB]] | |||
* [[ALT1]] | |||
=== External Links === | === External Links === | ||
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[[Category:Super FX]] | [[Category:Super FX]] | ||
[[Category:Data Transfer Instructions]] | [[Category:Data Transfer Instructions]] | ||
[[Category:Expects Sreg/Dreg Prearranged]] | |||
Latest revision as of 05:20, 16 July 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | ROM Speed | RAM Speed | Cache Speed | ||
| Implied Indirect | 3D3m | 2 bytes | 6 to 9 cycles | 8 to 14 cycles | 2 to 5 cycles | ||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | . | . | . | . | ||
STB (Store Byte) is a Super FX instruction that stores the low byte of the source register to the Game Pak. STB expects the target address to be in the Rm register. The bank must be specified with RAMB.
The operand may be any register from R0 to R11. The number of cycles can vary because of the RAM buffer.
The source register should be specified in advance using WITH or FROM. Otherwise, R0 serves as the default.
The ALT0 state is restored.
Syntax
STB (Rm)
Example
Let:
Sreg : R5 R5 = 216ch R8 = 9a34h RAMBR = 70h
After STB (R8) is executed:
(70:9A34h) = 6ch
See Also
External Links
- Official Super Nintendo development manual on STB: 9.83 on page 2-9-115