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STW (Super FX): Difference between revisions

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(The operand may be any register from R<sub>0</sub> to R<sub>11</sub>.)
 
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'''STW''' (Store Word) is a [[Super FX]] instruction that stores the value of the [[source register]] to the [[Game Pak]].
'''STW''' (Store Word) is a [[Super FX]] instruction that stores the value of the [[source register]] to the [[Game Pak]].  The bank must be specified with [[RAMB]].


The exact number of cycles varies because STW utilizes the [[RAM buffer]].
The exact number of cycles varies because STW utilizes the [[RAM buffer]].


The operand may be any register from R<sub>0</sub> to R<sub>11</sub>.
The operand may be any register from R<sub>0</sub> to R<sub>11</sub>.
The source register should be specified in advance using [[WITH]] or [[FROM]].  Otherwise, R<sub>0</sub> serves as the default.
The [[ALT0]] state is restored.
==== Syntax ====
<pre>
STW (Rm)
</pre>
==== Example ====
Let:
S<sub>reg</sub> : R<sub>10</sub>
R<sub>10</sub> = 9326h
R<sub>2</sub> : 5872h
RAMBR = 70h
After STW (R<sub>2</sub>) is executed:
(70:5872h) = 26h
(70:5873h) = 93h


=== See Also ===
=== See Also ===
* [[STB]]
* [[STB]]
* [[RAMB]]
* [[LDW]]


=== External Links ===
=== External Links ===
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[[Category:Super FX]]
[[Category:Super FX]]
[[Category:Data Transfer Instructions]]
[[Category:Data Transfer Instructions]]
[[Category:Expects Sreg/Dreg Prearranged]]

Latest revision as of 05:20, 16 July 2024

Basic Info
Addressing Mode Opcode Length ROM Speed RAM Speed Cache Speed
Implied Indirect 3m 1 byte 3 to 8 cycles 7 to 11 cycles 1 to 6 cycles
Flags Affected
B ALT1 ALT2 O/V S CY Z
0 0 0 . . . .

STW (Store Word) is a Super FX instruction that stores the value of the source register to the Game Pak. The bank must be specified with RAMB.

The exact number of cycles varies because STW utilizes the RAM buffer.

The operand may be any register from R0 to R11.

The source register should be specified in advance using WITH or FROM. Otherwise, R0 serves as the default.

The ALT0 state is restored.

Syntax

STW (Rm)

Example

Let:

Sreg : R10
R10 = 9326h
R2 : 5872h
RAMBR = 70h

After STW (R2) is executed:

(70:5872h) = 26h
(70:5873h) = 93h

See Also

External Links