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BIC (Super FX): Difference between revisions

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'''BIC''' (BIt Clear mask) is a [[Super FX]] instruction that performs a logical AND between the [[source register]] and the 1's complement of the operand.  The conjunction is stored in the [[destination register]].
'''BIC''' (BIt Clear mask) is a [[Super FX]] instruction that performs a logical AND between the [[source register]] and the 1's complement of the operand.  The conjunction is stored in the [[destination register]].
The [[ALT0]] state is restored.
The source and destination registers should be specified in advance using [[WITH]], [[FROM]], or [[TO]].  Otherwise, R<sub>0</sub> serves as the default.


==== Syntax ====
==== Syntax ====
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BIC #n
BIC #n
</pre>
</pre>
==== Example 1 ====
Let:
S<sub>reg</sub> : R<sub>2</sub>
D<sub>reg</sub> : R<sub>0</sub>
R<sub>2</sub> = 75ceh (0111 0101 1100 1110b)
R<sub>1</sub> = 3846h (0011 1000 0100 0110b)
After executing BIC R<sub>1</sub>:
R<sub>0</sub> = 4588h (0100 0101 1000 1000b)
==== Example 2 ====
Let:
S<sub>reg</sub> : R<sub>4</sub>
D<sub>reg</sub> : R<sub>5</sub>
R<sub>4</sub> = 364bh (0011 0110 0100 1011b)
After BIC #F is executed:
R<sub>5</sub> = 3640h (0011 0110 0100 0000b)


=== See Also ===
=== See Also ===
* [[AND (Super FX)]]
* [[AND (Super FX)]]
* [[OR (Super FX)]]
* [[OR (Super FX)]]
* [[XOR (Super FX)]]
* [[ALT1]]
* [[ALT3]]


=== External Links ===
=== External Links ===
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[[Category:ASM]]
[[Category:ASM]]
[[Category:Super FX]]
[[Category:Super FX]]
[[Category:Logical Operation Instructions]]
[[Category:Expects Sreg/Dreg Prearranged]]

Latest revision as of 18:38, 30 July 2024

Basic Info
Addressing Mode Opcode Length ROM Speed RAM Speed Cache Speed
Implied (type 1) 3D7n 2 bytes 6 cycles 6 cycles 2 cycles
Immediate 3F7n 2 bytes 6 cycles 6 cycles 2 cycles
Flags Affected
B ALT1 ALT2 O/V S CY Z
0 0 0 . S . Z

BIC (BIt Clear mask) is a Super FX instruction that performs a logical AND between the source register and the 1's complement of the operand. The conjunction is stored in the destination register.

The ALT0 state is restored.

The source and destination registers should be specified in advance using WITH, FROM, or TO. Otherwise, R0 serves as the default.

Syntax

BIC Rn
BIC #n

Example 1

Let:

Sreg : R2
Dreg : R0
R2 = 75ceh (0111 0101 1100 1110b)
R1 = 3846h (0011 1000 0100 0110b)

After executing BIC R1:

R0 = 4588h (0100 0101 1000 1000b)

Example 2

Let:

Sreg : R4
Dreg : R5
R4 = 364bh (0011 0110 0100 1011b)

After BIC #F is executed:

R5 = 3640h (0011 0110 0100 0000b)

See Also

External Links