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BRK: Difference between revisions

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|N
|[[Negative Flag|N]]
|V
|[[Overflow Flag|V]]
|M
|[[M Flag|M]]
|X / B
|[[X Flag|X]] / [[Break Flag|B]]
|D
|[[D Flag|D]]
|I
|[[I Flag|I]]
|Z
|[[Zero Flag|Z]]
|C
|[[Carry Flag|C]]
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|[[65c816 native mode]]
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'''BRK''' (Break) is a 65x instruction designed to trigger a software interrupt.  The byte following the opcode is called the [[Signature Byte]].  The state of the [[interrupt disable flag]] has no effect on the behavior of BRK.
'''BRK''' (Break) is a 65x instruction that triggers a non-maskable software interrupt ([[Non-Maskable Interrupt|NMI]]).  The byte following the opcode is called the [[signature byte]].  The state of the [[interrupt disable flag]] has no effect on the behavior of BRK although it will be set after BRK runs.


Control is routed to the BRK handler, whose address is stored at the BRK vectorIn native mode, this vector is at $00:FFE6. In emulation mode, this vector is at $FFFE.
Control is routed to the BRK handler, whose address is stored at the BRK vector:
* In native mode, this vector is at $00:FFE6.
* In emulation mode, this vector is at $FFFE.
 
The [[PBR]] is cleared, but in [[native mode]] its previous value is pushed to the [[stack]].


==== Syntax ====
==== Syntax ====
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</pre>
</pre>


===== Cycle Skipped =====
==== Cycle Skipped ====
BRK takes one fewer cycle in [[emulation mode]] as it doesn't need to push the [[program counter bank register]] to the [[stack]].
BRK takes one fewer cycle in [[emulation mode]] as it doesn't need to push the [[program counter bank register]] to the [[stack]].
If the signature byte was omitted from the assembler source, then it ends up serving double duty as the opcode of the next instruction.  In this case the [[interrupt handler]] must decrement the [[return address]] on the [[stack]] so that the eventual [[RTI]] does not cause [[derailment]].
[[File:brk.png]]
BRK used to be considered a one-byte instruction in an early datasheet.


=== See Also ===
=== See Also ===
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* [[IRQ]]
* [[IRQ]]
* [[COP]]
* [[COP]]
* [[WDM]]
* [[CLD]]
* [[SEI]]


=== External Links ===
=== External Links ===
* [[Eyes & Lichty]] page 436, on BRK: https://archive.org/details/0893037893ProgrammingThe65816/page/n462
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/436 page 436] on BRK
* Figure 13.3.  illustration. Lbid. [https://archive.org/details/0893037893ProgrammingThe65816/page/n282 page 256]
* Figure 13.3, Break Signature Byte Illustration, lbid, [https://archive.org/details/0893037893ProgrammingThe65816/page/n282 page 256]
* [[Labiak]] page 126 on BRK: https://archive.org/details/Programming_the_65816/page/n136
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n136 page 126] on BRK
* [[MCS6500 Manual]] page 144 on BRK: https://archive.org/details/mos_microcomputers_programming_manual/page/n164
* 9.11 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n164 page 144] on BRK
* [[Carr]] page 252 on BRK: https://archive.org/details/6502UsersManual/page/n265
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n265 page 252] on BRK
* [[Leventhal]] page 3-49 on BRK: https://archive.org/details/6502-assembly-language-programming/page/n98
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n98 page 3-49] on BRK
* snes9x implementation of BRK: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2547
* snes9x implementation of BRK: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2547
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#BRK
* https://undisbeliever.net/snesdev/65816-opcodes.html#software-interrupts


[[Category:ASM]]
[[Category:ASM]]

Latest revision as of 02:03, 23 August 2024

Basic Info
Addressing Mode Opcode Length Speed
Stack (Interrupt) 00 2 bytes 8 cycles*
Flags Affected
N V M X / B D I Z C
65c816 native mode . . . . 0 1 . .
6502 emulation mode . . . 1 0 1 . .

BRK (Break) is a 65x instruction that triggers a non-maskable software interrupt (NMI). The byte following the opcode is called the signature byte. The state of the interrupt disable flag has no effect on the behavior of BRK although it will be set after BRK runs.

Control is routed to the BRK handler, whose address is stored at the BRK vector:

  • In native mode, this vector is at $00:FFE6.
  • In emulation mode, this vector is at $FFFE.

The PBR is cleared, but in native mode its previous value is pushed to the stack.

Syntax

BRK
BRK sig

Cycle Skipped

BRK takes one fewer cycle in emulation mode as it doesn't need to push the program counter bank register to the stack.

If the signature byte was omitted from the assembler source, then it ends up serving double duty as the opcode of the next instruction. In this case the interrupt handler must decrement the return address on the stack so that the eventual RTI does not cause derailment.

brk.png

BRK used to be considered a one-byte instruction in an early datasheet.

See Also

External Links