AND

Basic Info
Addressing Mode	Opcode	Length	Speed
Immediate	29	2/3 bytes	2 cycles*
Absolute	2D	3 bytes	4 cycles*
Absolute Long	2F	4 bytes	5 cycles*
Direct Page	25	2 bytes	3 cycles*
Direct Page Indirect	32	2 bytes	5 cycles*
Direct Page Indirect Long	27	2 bytes	6 cycles*
Absolute Indexed by X	3D	3 bytes	4 cycles*
Absolute Long Indexed by X	3F	4 bytes	5 cycles*
Absolute Indexed by Y	39	3 bytes	4 cycles*
Direct Page Indexed by X	35	2 bytes	4 cycles*
Direct Page Indexed Indirect by X	21	2 bytes	6 cycles*
Direct Page Indirect Indexed by Y	31	2 bytes	5 cycles*
Direct Page Indirect Long Indexed by Y	37	2 bytes	6 cycles*
Stack Relative	23	2 bytes	4 cycles*
Stack Relative Indirect Indexed by Y	33	2 bytes	7 cycles*

Flags Affected
N	V	M	X	D	I	Z	C
N	.	.	.	.	.	Z	.

AND is a 65x instruction that performs a logical AND. The conjunction is stored in the accumulator. The size of the accumulator determines how much data is ANDed.

Syntax

AND #const
AND addr
AND long
AND dp
AND (dp)
AND [dp]
AND addr, X
AND long, X
AND addr, Y
AND dp, X
AND (dp, X)
AND (dp), Y
AND [dp], Y
AND sr, S
AND (sr, S), Y

Cycle Penalties

• In all addressing modes, AND takes one extra cycle when the accumulator is 16 bits wide.
• In direct page addressing modes only, AND takes an extra cycle if the low byte of the direct page register is nonzero.
• In both Absolute Indexed addressing modes and DP Indirect Indexed by Y admodes, AND takes an extra cycle if adding the index crosses a page boundary.

See Also

• ORA
• EOR
• BIT
• AND (SPC700)
• AND (Super FX)

External Links

• Eyes & Lichty, page 425 on AND
• Labiak, page 116 on AND
• 2.2.4.1 on MCS6500 Manual, page 20 on AND
• B-3, lbid.
• Carr, page 246 on AND
• Leventhal, page 3-40 on AND
• undisbeliever on AND: https://undisbeliever.net/snesdev/65816-opcodes.html#and-and-accumulator-with-memory
• Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#AND
• Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.1.2.1