We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS
LDW (Super FX): Difference between revisions
From SnesLab
(added example) |
(→See Also: STW) |
||
| (5 intermediate revisions by the same user not shown) | |||
| Line 26: | Line 26: | ||
|[[Sign Flag|S]] | |[[Sign Flag|S]] | ||
|[[CY]] | |[[CY]] | ||
|Z | |[[Zero Flag|Z]] | ||
|+ | |+ | ||
|0 | |0 | ||
| Line 37: | Line 37: | ||
|} | |} | ||
'''LDW''' (Load Word) is a [[Super FX]] instruction that loads one word from the [[Game Pak]] into the [[destination register]]. | '''LDW''' (Load Word) is a [[Super FX]] instruction that loads one word from the [[Game Pak]] into the [[destination register]]. The cycle times recorded here include the time spent while the load is happening, when the GSU is in the wait state. | ||
The [[ALT0]] state is restored. | |||
The destination registers should be specified in advance using [[WITH]] or [[TO]]. Otherwise, R<sub>0</sub> serves as the default. | |||
==== Syntax ==== | ==== Syntax ==== | ||
| Line 56: | Line 60: | ||
=== See Also === | === See Also === | ||
* [[LDB]] | * [[LDB]] | ||
* [[STW]] | |||
* [[RAMB]] | * [[RAMB]] | ||
| Line 64: | Line 69: | ||
[[Category:Super FX]] | [[Category:Super FX]] | ||
[[Category:Data Transfer Instructions]] | [[Category:Data Transfer Instructions]] | ||
[[Category:Expects Sreg/Dreg Prearranged]] | |||
Latest revision as of 05:20, 16 July 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | ROM Speed | RAM Speed | Cache Speed | ||
| Implied Indirect | 4m | 1 byte | 10 cycles | 12 cycles | 7 cycles | ||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | . | . | . | . | ||
LDW (Load Word) is a Super FX instruction that loads one word from the Game Pak into the destination register. The cycle times recorded here include the time spent while the load is happening, when the GSU is in the wait state.
The ALT0 state is restored.
The destination registers should be specified in advance using WITH or TO. Otherwise, R0 serves as the default.
Syntax
LDW (Rm)
where m can be from 0~11
Example
Let:
Dreg : R5 R3 = 6480h (70:6480h) = C0h RAMBR = 70h
After executing LDW (R3):
R5 = C02eh
See Also
External Links
- Official Super Nintendo development manual on LDW: 9.46 on Page 2-9-66 of Book II