We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS

MULT (Super FX): Difference between revisions

From SnesLab
Jump to: navigation, search
(added example 1)
(made flags affected more prominent)
 
(5 intermediate revisions by the same user not shown)
Line 33: Line 33:
|[[Sign Flag|S]]
|[[Sign Flag|S]]
|[[CY]]
|[[CY]]
|Z
|[[Zero Flag|Z]]
|+
|+
|0
|0
Line 39: Line 39:
|0
|0
|.
|.
|
|S
|.
|.
|
|Z
|}
|}


Line 49: Line 49:


The exact number of cycles depends on the state of the [[CFGR]] register.
The exact number of cycles depends on the state of the [[CFGR]] register.
The [[ALT0]] state is restored.
The source and destination registers should be specified in advance using [[WITH]], [[FROM]], or [[TO]].  Otherwise, R<sub>0</sub> serves as the default.


==== Syntax ====
==== Syntax ====
Line 64: Line 68:
After executing MULT R<sub>1</sub>:
After executing MULT R<sub>1</sub>:
  R<sub>2</sub> = 0961h
  R<sub>2</sub> = 0961h
==== Example 2 ====
Let:
S<sub>reg</sub> : R<sub>3</sub>
D<sub>reg</sub> : R<sub>4</sub>
R<sub>3</sub> = 95c6h
After executing MULT #9:
R<sub>4</sub> = fdf6h


=== See Also ===
=== See Also ===
Line 80: Line 92:
[[Category:Arithmetic Operation Instructions]]
[[Category:Arithmetic Operation Instructions]]
[[Category:Two-byte Instructions]]
[[Category:Two-byte Instructions]]
[[Category:Expects Sreg/Dreg Prearranged]]

Latest revision as of 19:22, 30 July 2024

Basic Info
Addressing Mode Opcode Length ROM Speed RAM Speed Cache Speed
Implied (type 1) 8n 1 byte 3 or 5 cycles 3 or 5 cycles 1 or 2 cycles
Immediate 3E8n 2 bytes 6 or 8 cycles 6 or 8 cycles 2 or 3 cycles
Flags Affected
B ALT1 ALT2 O/V S CY Z
0 0 0 . S . Z

MULT is a Super FX instruction that performs a signed multiplication. One of the factors is the low byte of the source register. The other factor may be any register from R0 to R15 or an immediate int from 0 to 15. The product is stored in the destination register.

MULT utilizes the 8-bit multiplier only once, so it is fast.[2]

The exact number of cycles depends on the state of the CFGR register.

The ALT0 state is restored.

The source and destination registers should be specified in advance using WITH, FROM, or TO. Otherwise, R0 serves as the default.

Syntax

MULT Rn
MULT #n

Example 1

Let:

Sreg : R5
Dreg : R2
R5 = 52cfh
R1 = 63cfh

After executing MULT R1:

R2 = 0961h

Example 2

Let:

Sreg : R3
Dreg : R4
R3 = 95c6h

After executing MULT #9:

R4 = fdf6h

See Also

External Links

  1. Official Nintendo documentation on MULT: 9.66 on Page 2-9-93 of Book II
  2. 8.2 "Multiplication Instructions" on page 2-8-16 of Book II, lbid.