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ASR (Super FX): Difference between revisions

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'''ASR''' (Arithmetic Shift Right) is a [[Super FX]] instruction that shifts all bits of the [[source register]]'s value to the right one bit while also leaving the most significant bit unchanged, storing the result in the [[destination register]].  Bit 0 is shifted into [[CY]].
'''ASR''' (Arithmetic Shift Right) is a [[Super FX]] instruction that shifts all bits of the [[source register]]'s value to the right one bit while also leaving the most significant bit unchanged, storing the result in the [[destination register]].  Bit 0 is shifted into [[CY]].
The [[ALT0]] state is restored.
The source and destination registers should be specified in advance using [[WITH]], [[FROM]], or [[TO]].  Otherwise, R<sub>0</sub> serves as the default.


==== Syntax ====
==== Syntax ====
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[[File:gsu_asr.png]]
[[File:gsu_asr.png]]
The source register itself is not modified despite the arrows in the above image.


=== See Also ===
=== See Also ===
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* [[LSR]]
* [[LSR]]
* [[DIV2]]
* [[DIV2]]
* [[ROR (Super FX)]]
* [[ROR (SPC700)]]
* [[ROR]]


=== External Links ===
=== External Links ===

Latest revision as of 02:04, 22 August 2024

Basic Info
Addressing Mode Opcode Length ROM Speed RAM Speed Cache Speed
Implied (type 1) 96 1 byte 3 cycles 3 cycles 1 cycle
Flags Affected
B ALT1 ALT2 O/V S CY Z
0 0 0 . S CY Z

ASR (Arithmetic Shift Right) is a Super FX instruction that shifts all bits of the source register's value to the right one bit while also leaving the most significant bit unchanged, storing the result in the destination register. Bit 0 is shifted into CY.

The ALT0 state is restored.

The source and destination registers should be specified in advance using WITH, FROM, or TO. Otherwise, R0 serves as the default.

Syntax

ASR

Example

Let:

Sreg : R10
Dreg : R1
CY = 0
R10 = 4f7bh (0100 1111 0111 1011b)

After executing ASR:

CY = 1
R1 = 27bdh (0010 0111 1011 1101b)

gsu asr.png

The source register itself is not modified despite the arrows in the above image.

See Also

External Links