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ROL (Super FX): Difference between revisions
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|[[Sign Flag|S]] | |[[Sign Flag|S]] | ||
|[[CY]] | |[[CY]] | ||
|Z | |[[Zero Flag|Z]] | ||
|+ | |+ | ||
|0 | |0 | ||
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|0 | |0 | ||
|. | |. | ||
| | |S | ||
| | |CY | ||
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|} | |} | ||
'''ROL''' (Rotate Left) is a [[Super FX]] instruction that rotates the [[source register]] and [[CY|carry flag]] one bit to the left into the [[destination register]]. | '''ROL''' (Rotate Left) is a [[Super FX]] instruction that rotates the value of the [[source register]] and [[CY|carry flag]] one bit to the left into the [[destination register]]. A total of 17 bits participate in the rotation. | ||
The [[ALT0]] state is restored. | |||
The source and destination registers should be specified in advance using [[WITH]], [[FROM]], or [[TO]]. Otherwise, R<sub>0</sub> serves as the default. | |||
==== Syntax ==== | ==== Syntax ==== | ||
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ROL | ROL | ||
</pre> | </pre> | ||
==== Example ==== | |||
Let: | |||
S<sub>reg</sub> : R<sub>8</sub> | |||
D<sub>reg</sub> : R<sub>4</sub> | |||
R<sub>8</sub> = 1d4bh (0001 1101 0100 1011b) | |||
CY = 1 | |||
After executing ROL: | |||
R<sub>4</sub> = 3a97h (0011 1010 1001 0111b) | |||
CY = 0 | |||
[[File:gsu_rol.png]] | [[File:gsu_rol.png]] | ||
The source register itself is not modified despite the arrows in the above image. | |||
=== See Also === | === See Also === | ||
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* [[ROL]] | * [[ROL]] | ||
* [[ROL (SPC700)]] | * [[ROL (SPC700)]] | ||
* [[LSR (Super FX)]] | |||
* [[ASR (Super FX)]] | |||
=== External Links === | === External Links === | ||
Latest revision as of 02:58, 22 August 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | ROM Speed | RAM Speed | Cache Speed | ||
| Implied (type 1) | 04 | 1 byte | 3 cycles | 3 cycles | 1 cycle | ||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | . | S | CY | Z | ||
ROL (Rotate Left) is a Super FX instruction that rotates the value of the source register and carry flag one bit to the left into the destination register. A total of 17 bits participate in the rotation.
The ALT0 state is restored.
The source and destination registers should be specified in advance using WITH, FROM, or TO. Otherwise, R0 serves as the default.
Syntax
ROL
Example
Let:
Sreg : R8 Dreg : R4 R8 = 1d4bh (0001 1101 0100 1011b) CY = 1
After executing ROL:
R4 = 3a97h (0011 1010 1001 0111b) CY = 0
The source register itself is not modified despite the arrows in the above image.
See Also
External Links
- Official Nintendo documentation on ROL: Page 2-9-102 of Book II
- example: page 2-9-103, lbid.