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CACHE (Super FX): Difference between revisions
From SnesLab
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=== External Links === | === External Links === | ||
* Official Nintendo documentation on CACHE: 9.27 on [https://archive.org/details/SNESDevManual/book2/page/n194 page 2-9-38 of Book II] | * Official Nintendo documentation on CACHE: 9.27 on [https://archive.org/details/SNESDevManual/book2/page/n194 page 2-9-38 of Book II] | ||
* [https://archive.org/details/SNESDevManual/book2/page/n135 page 2-7-1 of Book II] | * cautions for 7.1.1 on [https://archive.org/details/SNESDevManual/book2/page/n135 page 2-7-1 of Book II] | ||
[[Category:ASM]] | [[Category:ASM]] | ||
Latest revision as of 01:47, 12 August 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | ROM Speed | RAM Speed | Cache Speed | ||
| Implied (type 2) | 02 | 1 byte | 3 or 4 cycles | 3 or 4 cycles | 1 cycle | ||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | . | . | . | . | ||
CACHE is a Super FX instruction that might reset all cache flags. If the cache base register is equal to R15 & 0fff0h, nothing happens. Otherwise, set the cache base register to R15 & 0fff0h and reset all cache flags.
The ALT0 state is restored.
Syntax
CACHE
See Also
External Links
- Official Nintendo documentation on CACHE: 9.27 on page 2-9-38 of Book II
- cautions for 7.1.1 on page 2-7-1 of Book II