We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS
SlowROM: Difference between revisions
From SnesLab
(→See Also: waitstate) |
(added ROM access speed) |
||
| (One intermediate revision by the same user not shown) | |||
| Line 1: | Line 1: | ||
'''SlowROM''' is 2.68 Mhz. It is not as fast as [[FastROM]]. SlowROM is a property of the ROM chip itself and not the board it is soldered onto.<sup>[2]</sup> [[DMA]] always happens at SlowROM speed. When the [[5A22]] is operating at slowROM speed, there are 8 [[master clock]] cycles per CPU [[machine cycle]]. | '''SlowROM''' is 2.68 Mhz and its ROM access speed is 200ns. It is not as fast as [[FastROM]]. SlowROM is a property of the ROM chip itself and not the board it is soldered onto.<sup>[2]</sup> [[DMA]] always happens at SlowROM speed. When the [[5A22]] is operating at slowROM speed, there are 8 [[master clock]] cycles per CPU [[machine cycle]]. | ||
[[File:master_clock_divider_speeds.png]] | [[File:master_clock_divider_speeds.png]] | ||
| Line 6: | Line 6: | ||
* [[List of SlowROM Games]] | * [[List of SlowROM Games]] | ||
* [[Waitstate]] | * [[Waitstate]] | ||
* [[420Dh]] | |||
=== References === | === References === | ||
Latest revision as of 17:07, 19 August 2024
SlowROM is 2.68 Mhz and its ROM access speed is 200ns. It is not as fast as FastROM. SlowROM is a property of the ROM chip itself and not the board it is soldered onto.[2] DMA always happens at SlowROM speed. When the 5A22 is operating at slowROM speed, there are 8 master clock cycles per CPU machine cycle.
See Also
References
- Near, https://forums.nesdev.org/viewtopic.php?t=9585
- Bregalad, lbid.