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ADSR Mode: Difference between revisions
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'''ADSR Mode''' is enabled when bit 7 of ADSR(1), which is located at 05h of [[DSPRAM]], is set. It makes the two bytes located at 05h and 06h operable. | '''ADSR Mode''' (Attack Decay Sustain Release) is enabled when bit 7 of ADSR(1), which is located at 05h of [[DSPRAM]], is set. It makes the two bytes located at 05h and 06h operable. | ||
=== References === | === References === | ||
* [https://archive.org/details/SNESDevManual/book1/page/n169 page 3-7-3 of Book I] of the official Super Nintendo development manual | * [https://archive.org/details/SNESDevManual/book1/page/n169 page 3-7-3 of Book I] of the official Super Nintendo development manual | ||
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Latest revision as of 20:02, 9 July 2024
ADSR Mode (Attack Decay Sustain Release) is enabled when bit 7 of ADSR(1), which is located at 05h of DSPRAM, is set. It makes the two bytes located at 05h and 06h operable.
References
- page 3-7-3 of Book I of the official Super Nintendo development manual