STX: Difference between revisions

Latest revision as of 06:41, 22 August 2024


Basic Info
Addressing Mode	Opcode	Length	Speed
Absolute	8E	3 bytes	4 cycles*
Direct Page	86	2 bytes	3 cycles*
Direct Page Indexed by Y	96	2 bytes	4 cycles*


Flags Affected
N	V	M	X	D	I	Z	C
.	.	.	.	.	.	.	.

STX (Store X) is a 65x instruction that stores the value of the X index register. If X is 16-bit, its high byte is stored to the effective address plus one.

No flags are affected.

Syntax

STX addr
STX dp
STX dp, Y

Cycle Penalties

STX takes one additional cycle when the index registers are 16 bits wide, in all addressing modes.
In both direct page addressing modes only, STX takes another additional cycle if the low byte of the direct page register is nonzero.

External Links

Eyes & Lichty, page 505, on STX
Labiak, page 186 on STX
7.2 on MCS6500 Manual, page 97 on STX
Carr, page 274 on STX
Leventhal, page 3-97 on STX
snes9x implementation of STX: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L1287
undisbeliever on STX: https://undisbeliever.net/snesdev/65816-opcodes.html#stx-store-index-register-x-to-memory
Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#STX

@@ Line 7: / Line 7: @@
 |'''Speed'''
 |+
-|absolute
+|[[Absolute]]
 |8E
 |3 bytes
-|4 cycles
+|4 cycles*
 |+
-|direct page
+|[[Direct Page Addressing|Direct Page]]
 |86
 |2 bytes
-|3 cycles
+|3 cycles*
 |+
-|direct page indexed Y
+|[[Direct Page Indexed by Y]]
 |96
 |2 bytes
-|4 cycles
+|4 cycles*
 |}
 {| class="wikitable" style="float:right;clear:right;width:30%"
-!colspan="9"|Flags Clobbered
+!colspan="9"|Flags Affected
 |+
-|N
+|[[Negative Flag|N]]
-|V
+|[[Overflow Flag|V]]
-|M
+|[[M Flag|M]]
-|X
+|[[X Flag|X]]
-|D
+|[[Decimal Flag|D]]
-|I
+|[[I Flag|I]]
-|Z
+|[[Zero Flag|Z]]
-|C
+|[[Carry Flag|C]]
 |+
 |.
@@ Line 45: / Line 45: @@
 |}
-'''STX''' (Store X) is a 65x instruction that stores the value of the [[X index register]].
+'''STX''' (Store X) is a 65x instruction that stores the value of the [[X index register]].  If X is 16-bit, its high byte is stored to the effective address plus one.
+No flags are affected.
+==== Syntax ====
+<pre>
+STX addr
+STX dp
+STX dp, Y
+</pre>
+==== Cycle Penalties ====
+* STX takes one additional cycle when the index registers are 16 bits wide, in all [[addressing modes]].
+* In both [[direct page addressing]] modes only, STX takes another additional cycle if the low byte of the [[direct page register]] is nonzero.
 === See Also ===
+* [[LDX]]
 * [[STA]]
 * [[STY]]
 * [[STZ]]
+* [[TXA]]
+* [[TXY]]
+* [[TXS]]
 === External Links ===
-* [[Eyes & Lichty]] page on STX: https://archive.org/details/0893037893ProgrammingThe65816/page/n531
+* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/505 page 505], on STX
-* [[Labiak]] page on STX: https://archive.org/details/Programming_the_65816/page/n195
+* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n196 page 186] on STX
-* [[MCS6500 Manual]] page on STX: https://archive.org/details/mos_microcomputers_programming_manual/page/n115
+* 7.2 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n115 page 97] on STX
-* [[Carr]] page on STX: https://archive.org/details/6502UsersManual/page/n287
+* [[Carr]], [https://archive.org/details/6502UsersManual/page/n287 page 274] on STX
-* [[Leventhal]] page on STX: https://archive.org/details/6502-assembly-language-programming/page/n146
+* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n146 page 3-97] on STX
 * snes9x implementation of STX: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L1287
 * undisbeliever on STX: https://undisbeliever.net/snesdev/65816-opcodes.html#stx-store-index-register-x-to-memory
+* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#STX
 [[Category:ASM]]
 [[Category:Group Two Instructions]]
 [[Category:Inherited from 6502]]
+[[Category:Load/Store Instructions]]