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ADSR Mode: Difference between revisions

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'''ADSR Mode''' is enabled when bit 7 of ADSR(1), which is located at 05h of [[DSPRAM]], is set.  It makes the two bytes located at 05h and 06h operable.
'''ADSR Mode''' (Attack Decay Sustain Release) is enabled when bit 7 of ADSR(1), which is located at 05h of [[DSPRAM]], is set.  It makes the two bytes located at 05h and 06h operable.


=== References ===
=== References ===

Latest revision as of 20:02, 9 July 2024

ADSR Mode (Attack Decay Sustain Release) is enabled when bit 7 of ADSR(1), which is located at 05h of DSPRAM, is set. It makes the two bytes located at 05h and 06h operable.

References