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Revision 1 CPU DMA crash: Difference between revisions
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Little is known about why the '''CPU revision 1 DMA crash''' happens. In 2015, Ramsis wrote a test rom to trigger it. [2] | Little is known about why the '''CPU revision 1 DMA crash''' happens. In 2015, Ramsis wrote a test rom to trigger it. <sup>[2]</sup> | ||
=== Trigger === | === Trigger === | ||
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=== References === | === References === | ||
# [https://archive.org/details/SNESDevManual/book1/page/n111 page 2-25-1 of Book I] of the official Super Nintendo development manual | # [https://archive.org/details/SNESDevManual/book1/page/n111 page 2-25-1 of Book I] of the official Super Nintendo development manual, the ICE mentioned likely stands for "[https://www.microcontrollertips.com/faq-what-is-ice/# In-Circuit Emulator]" | ||
# https://forums.nesdev.org/viewtopic.php?t=13280 | # https://forums.nesdev.org/viewtopic.php?t=13280 | ||
[[Category:SNES Hardware]] | [[Category:SNES Hardware]] | ||
Latest revision as of 19:40, 9 August 2023
Little is known about why the CPU revision 1 DMA crash happens. In 2015, Ramsis wrote a test rom to trigger it. [2]
Trigger
- kicking of an HDMA at about the same time that a General Purpose DMA finishes
Symptoms
Workarounds
- Use GPDMA only during vblank
- Make sure HDMA starts in the middle of a GPDMA data transfer
- Avoid HDMA
- Adjust the time at which GPDMA begins
- Decrease the number of bytes transferred during GPDMA
See Also
References
- page 2-25-1 of Book I of the official Super Nintendo development manual, the ICE mentioned likely stands for "In-Circuit Emulator"
- https://forums.nesdev.org/viewtopic.php?t=13280