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Cache Base Register: Difference between revisions

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The '''Cache Base Register''' exists on the [[Super FX]].
The '''Cache Base Register''' (CBR) exists on the [[Super FX]]. It is located at 303fh.  It is 12 bits in size.  (The remaining low 4 bits of 303eh return zero when read).
 
It is updated whenever [[CACHE]] or [[LJMP]] run.
 
=== Reference ===
* subparagraph 2.2.2.4 on [https://archive.org/details/SNESDevManual/book2/page/n98 page 2-2-4 of Book II] of the official Super Nintendo development manual


[[Category:Registers]]
[[Category:Registers]]
[[Category:Super FX]]
[[Category:Super FX]]

Latest revision as of 01:40, 12 August 2024

The Cache Base Register (CBR) exists on the Super FX. It is located at 303fh. It is 12 bits in size. (The remaining low 4 bits of 303eh return zero when read).

It is updated whenever CACHE or LJMP run.

Reference