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ROR (Super FX): Difference between revisions
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{| class="wikitable" style="float:right;clear:right;width: | {| class="wikitable" style="float:right;clear:right;width:50%" | ||
!colspan="8"|Basic Info | !colspan="8"|Basic Info | ||
|+ | |+ | ||
|'''Addressing Mode''' | |||
|'''Opcode''' | |'''Opcode''' | ||
|'''Length''' | |'''Length''' | ||
| Line 8: | Line 9: | ||
|'''Cache Speed''' | |'''Cache Speed''' | ||
|+ | |+ | ||
|[[Implied]] (type 1) | |||
|97 | |97 | ||
|1 byte | |1 byte | ||
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!colspan="9"|Flags Affected | !colspan="9"|Flags Affected | ||
|+ | |+ | ||
|B | |[[B Flag|B]] | ||
|ALT1 | |[[ALT1]] | ||
|ALT2 | |[[ALT2]] | ||
|O/V | |[[O/V]] | ||
|S | |[[Sign Flag|S]] | ||
|CY | |[[CY]] | ||
|Z | |[[Zero Flag|Z]] | ||
|+ | |+ | ||
|0 | |0 | ||
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|0 | |0 | ||
|. | |. | ||
| | |S | ||
| | |CY | ||
| | |Z | ||
|} | |} | ||
'''ROR''' (Rotate Right) is a [[Super FX]] instruction that rotates the [[source register]] and [[carry flag]] into the [[destination register]]. | '''ROR''' (Rotate Right) is a [[Super FX]] instruction that rotates the value of the [[source register]] and [[CY|carry flag]] one bit to the right into the [[destination register]]. Bit 0 of S<sub>reg</sub> is shifted into the carry flag. A total of 17 bits participate in the rotation. | ||
The [[ALT0]] state is restored. | |||
The source and destination registers should be specified in advance using [[WITH]], [[FROM]], or [[TO]]. Otherwise, R<sub>0</sub> serves as the default. | |||
==== Syntax ==== | |||
<pre> | |||
ROR | |||
</pre> | |||
==== Example ==== | |||
Let: | |||
S<sub>reg</sub> : R<sub>10</sub> | |||
D<sub>reg</sub> : R<sub>12</sub> | |||
CY = 1 | |||
R<sub>10</sub> = 1d4bh (0001 1101 0100 1011b) | |||
After executing ROR: | |||
CY = 1 | |||
R<sub>12</sub> = 8ea5h (1000 1110 1010 0101b) | |||
[[File:gsu_ror.png]] | |||
The source register itself is not modified despite the arrows in the above image. | |||
=== See Also === | === See Also === | ||
* [[ROL (Super FX)]] | * [[ROL (Super FX)]] | ||
* [[ROR]] | * [[ROR]] | ||
* [[LSR (Super FX)]] | |||
* [[ASR (Super FX)]] | |||
=== External Links === | === External Links === | ||
* Official Nintendo documentation on ROR: [https://archive.org/details/SNESDevManual/book2/page/n261 | * Official Nintendo documentation on ROR: 9.76 on [https://archive.org/details/SNESDevManual/book2/page/n261 page 2-9-105 of Book II] | ||
* example: [https://archive.org/details/SNESDevManual/book2/page/n262 page 2-9-106], lbid. | |||
[[Category:Super FX]] | [[Category:Super FX]] | ||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category:Shift Instructions]] | [[Category:Shift Instructions]] | ||
[[Category:Expects Sreg/Dreg Prearranged]] | |||
Latest revision as of 02:20, 22 August 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | ROM Speed | RAM Speed | Cache Speed | ||
| Implied (type 1) | 97 | 1 byte | 3 cycles | 3 cycles | 1 cycle | ||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | . | S | CY | Z | ||
ROR (Rotate Right) is a Super FX instruction that rotates the value of the source register and carry flag one bit to the right into the destination register. Bit 0 of Sreg is shifted into the carry flag. A total of 17 bits participate in the rotation.
The ALT0 state is restored.
The source and destination registers should be specified in advance using WITH, FROM, or TO. Otherwise, R0 serves as the default.
Syntax
ROR
Example
Let:
Sreg : R10 Dreg : R12 CY = 1 R10 = 1d4bh (0001 1101 0100 1011b)
After executing ROR:
CY = 1 R12 = 8ea5h (1000 1110 1010 0101b)
The source register itself is not modified despite the arrows in the above image.
See Also
External Links
- Official Nintendo documentation on ROR: 9.76 on page 2-9-105 of Book II
- example: page 2-9-106, lbid.