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LMULT (Super FX): Difference between revisions
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!colspan="8"|Basic Info | !colspan="8"|Basic Info | ||
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|'''Addressing Mode''' | |||
|'''Opcode''' | |'''Opcode''' | ||
|'''Length''' | |'''Length''' | ||
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|'''Cache Speed''' | |'''Cache Speed''' | ||
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|[[Implied]] (type 1) | |||
|3D9F | |3D9F | ||
|2 bytes | |2 bytes | ||
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{| class="wikitable" style="float:right;clear:right;width:30%" | {| class="wikitable" style="float:right;clear:right;width:30%" | ||
!colspan="9"|Flags | !colspan="9"|Flags Affected | ||
|+ | |+ | ||
|B | |[[B Flag|B]] | ||
|ALT1 | |[[ALT1]] | ||
|ALT2 | |[[ALT2]] | ||
|O/V | |[[O/V]] | ||
|S | |[[Sign Flag|S]] | ||
|CY | |[[CY]] | ||
|Z | |[[Zero Flag|Z]] | ||
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|0 | |0 | ||
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|0 | |0 | ||
|. | |. | ||
| | |S | ||
| | |CY | ||
| | |Z | ||
|} | |} | ||
'''LMULT''' is a signed multiplication [[Super FX]] instruction. The exact speed depends on the state of the [[CFGR]] register. | '''LMULT''' is a signed multiplication [[Super FX]] instruction. The two 16-bit factors are the [[source register]] and R<sub>6</sub>. The exact speed depends on the state of the [[CFGR]] register. | ||
The upper 16 bits of the product are stored in the [[destination register]]. The lower 16 bits of the product are stored in R<sub>4</sub>. | |||
LMULT utilizes the 8-bit multiplier four times.<sup>[3]</sup> | |||
LMULT shares its multiplication circuit with [[FMULT]]. | |||
If R<sub>4</sub> is specified as the destination register, the product will be invalid.<sup>[1]</sup> | |||
The [[ALT0]] state is restored. | |||
The source and destination registers should be specified in advance using [[WITH]], [[FROM]], or [[TO]]. Otherwise, R<sub>0</sub> serves as the default. | |||
==== Syntax ==== | |||
LMULT | |||
==== Example ==== | |||
Let: | |||
S<sub>reg</sub> : R<sub>9</sub> | |||
D<sub>reg</sub> : R<sub>8</sub> | |||
R<sub>9</sub> = b556h | |||
R<sub>6</sub> = daabh | |||
After LMULT is executed: | |||
R<sub>8</sub> = 0ae3h | |||
R<sub>4</sub> = 5c72h | |||
=== See Also === | === See Also === | ||
* [[UMULT]] | * [[UMULT]] | ||
* [[MULT]] | |||
* [[Partial Product Buffer]] | |||
* [[DIV2]] | |||
* [[ALT1]] | |||
=== External Links === | === External Links === | ||
# Official Nintendo documentation on LMULT: 9.52 on [https://archive.org/details/SNESDevManual/book2/page/n229 page 2-9-73 of Book II] | |||
# example: [https://archive.org/details/SNESDevManual/book2/page/n230 page 2-9-74 of Book II], lbid. | |||
# [https://archive.org/details/SNESDevManual/book2/page/n155 page 2-8-16 of Book II], lbid. | |||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category:Super FX]] | [[Category:Super FX]] | ||
[[Category:Expects Sreg/Dreg Prearranged]] | |||
Latest revision as of 19:27, 30 July 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | ROM Speed | RAM Speed | Cache Speed | ||
| Implied (type 1) | 3D9F | 2 bytes | 10 or 14 cycles | 10 or 14 cycles | 5 or 9 cycles | ||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | . | S | CY | Z | ||
LMULT is a signed multiplication Super FX instruction. The two 16-bit factors are the source register and R6. The exact speed depends on the state of the CFGR register.
The upper 16 bits of the product are stored in the destination register. The lower 16 bits of the product are stored in R4.
LMULT utilizes the 8-bit multiplier four times.[3]
LMULT shares its multiplication circuit with FMULT.
If R4 is specified as the destination register, the product will be invalid.[1]
The ALT0 state is restored.
The source and destination registers should be specified in advance using WITH, FROM, or TO. Otherwise, R0 serves as the default.
Syntax
LMULT
Example
Let:
Sreg : R9 Dreg : R8 R9 = b556h R6 = daabh
After LMULT is executed:
R8 = 0ae3h R4 = 5c72h
See Also
External Links
- Official Nintendo documentation on LMULT: 9.52 on page 2-9-73 of Book II
- example: page 2-9-74 of Book II, lbid.
- page 2-8-16 of Book II, lbid.