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PLX: Difference between revisions
From SnesLab
(→See Also: PHX) |
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|'''Speed''' | |'''Speed''' | ||
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| | |[[Stack Addressing|Stack]] (Pull) | ||
|FA | |FA | ||
|1 byte | |1 byte | ||
|4 cycles | |4 cycles* | ||
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{| class="wikitable" style="float:right;clear:right;width:30%" | {| class="wikitable" style="float:right;clear:right;width:30%" | ||
!colspan="9"|Flags | !colspan="9"|Flags Affected | ||
|+ | |||
|[[Negative Flag|N]] | |||
|[[Overflow Flag|V]] | |||
|[[M Flag|M]] | |||
|[[X Flag|X]] | |||
|[[Decimal Flag|D]] | |||
|[[I Flag|I]] | |||
|[[Zero Flag|Z]] | |||
|[[Carry Flag|C]] | |||
|+ | |+ | ||
|N | |N | ||
|. | |. | ||
|. | |. | ||
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| | |Z | ||
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'''PLX''' (PulL X) is a 65x instruction that pulls the value at the top of the [[stack]] into the [[X index register]]. | '''PLX''' (PulL X) is a 65x instruction that pulls the value at the top of the [[stack]] into the [[X index register]]. PLX increments the [[stack pointer]] before the pull. | ||
The Labiak textbook seems to have omitted the fact that according to the datasheet, PLX affects the [[zero flag]]. | |||
==== Syntax ==== | |||
<pre> | |||
PLX | |||
</pre> | |||
==== Cycle Penalty ==== | |||
* PLX takes one additional cycle if the index registers are 16 bits wide. | |||
=== See Also === | === See Also === | ||
| Line 41: | Line 51: | ||
* [[PLA]] | * [[PLA]] | ||
* [[PHX]] | * [[PHX]] | ||
* [[LDX]] | |||
=== External Links === | === External Links === | ||
* [[Eyes & Lichty]] | * [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/487 page 487] on PLX | ||
* [[Labiak]] | * [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n181 page 171] on PLX | ||
* snes9x implementation of PLX: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2156 | * snes9x implementation of PLX: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2156 | ||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category:65c02 additions]] | [[Category:65c02 additions]] | ||
[[Category:Pull Instructions]] | |||
[[Category:One-byte Instructions]] | |||
[[Category:Four-cycle Instructions]] | |||
Latest revision as of 17:39, 23 August 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | Speed | ||||
| Stack (Pull) | FA | 1 byte | 4 cycles* | ||||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| N | V | M | X | D | I | Z | C | |
| N | . | . | . | . | . | Z | . | |
PLX (PulL X) is a 65x instruction that pulls the value at the top of the stack into the X index register. PLX increments the stack pointer before the pull.
The Labiak textbook seems to have omitted the fact that according to the datasheet, PLX affects the zero flag.
Syntax
PLX
Cycle Penalty
- PLX takes one additional cycle if the index registers are 16 bits wide.
See Also
External Links
- Eyes & Lichty, page 487 on PLX
- Labiak, page 171 on PLX
- snes9x implementation of PLX: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2156