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BIT: Difference between revisions

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(added cycle penalties)
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|[[Immediate]]
|[[Immediate]]
|89
|89
|2 bytes
|2 bytes*
|2 cycles
|2 cycles*
|+
|+
|[[Absolute]]
|[[Absolute]]
|2C
|2C
|3 bytes
|3 bytes
|4 cycles
|4 cycles*
|+
|+
|[[Direct Page Addressing|Direct Page]]
|[[Direct Page Addressing|Direct Page]]
|24
|24
|2 bytes
|2 bytes
|3 cycles
|3 cycles*
|+
|+
|absolute indexed X
|absolute indexed X
|3C
|3C
|3 bytes
|3 bytes
|4 cycles
|4 cycles*
|+
|+
|direct page indexed X
|direct page indexed X
|34
|34
|2 bytes
|2 bytes
|4 cycles
|4 cycles*
|}
|}


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'''BIT''' is a 65x instruction that performs a logical AND operation between the [[accumulator]] and memory without storing the conjunction.
'''BIT''' is a 65x instruction that performs a logical AND operation between the [[accumulator]] and memory without storing the conjunction.
===== Cycle Penalties =====
* BIT takes an extra cycle when the accumulator is 16 bits wide, in all [[addressing modes]]
* In direct page addressing modes, BIT takes an extra cycle when the low byte of the [[direct page register]] is nonzero
* In [[Absolute Indexed, X Addressing]], BIT takes an extra cycle when adding the index crosses a page boundary


=== External Links ===
=== External Links ===

Revision as of 01:10, 22 November 2023

Basic Info
Addressing Mode Opcode Length Speed
Immediate 89 2 bytes* 2 cycles*
Absolute 2C 3 bytes 4 cycles*
Direct Page 24 2 bytes 3 cycles*
absolute indexed X 3C 3 bytes 4 cycles*
direct page indexed X 34 2 bytes 4 cycles*
Flags Affected
N V M X D I Z C
. . . . .

BIT is a 65x instruction that performs a logical AND operation between the accumulator and memory without storing the conjunction.

Cycle Penalties

External Links