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AND: Difference between revisions

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'''AND''' is a 65x instruction that performs a logical AND. In all [[addressing modes]], AND takes one extra cycle when the accumulator is 16 bits wide. In [[direct page addressing]] modes only, AND takes an extra cycle if the low byte of the [[direct page register]] is nonzero. In both [[Absolute Indexed]] addressing modes and DP Indirect Indexed by Y admodes, AND takes an extra cycle if adding the index crosses a page boundary.
'''AND''' is a 65x instruction that performs a logical AND.
 
===== Cycle Penalties =====
* In all [[addressing modes]], AND takes one extra cycle when the accumulator is 16 bits wide.
* In [[direct page addressing]] modes only, AND takes an extra cycle if the low byte of the [[direct page register]] is nonzero.
* In both [[Absolute Indexed]] addressing modes and DP Indirect Indexed by Y admodes, AND takes an extra cycle if adding the index crosses a page boundary.


=== See Also ===
=== See Also ===

Revision as of 03:09, 25 November 2023

Basic Info
Addressing Mode Opcode Length Speed
Immediate 29 2 bytes 2 cycles*
Absolute 2D 3 bytes 4 cycles*
Absolute Long 2F 4 bytes 5 cycles*
Direct Page 25 2 bytes 3 cycles*
Direct Page Indirect 32 2 bytes 5 cycles*
Direct Page Indirect Long 27 2 bytes 6 cycles*
absolute indexed by X 3D 3 bytes 4 cycles*
absolute long indexed by X 3F 4 bytes 5 cycles*
absolute indexed by Y 39 3 bytes 4 cycles*
direct page indexed by X 35 2 bytes 4 cycles*
direct page indirect indexed by X 21 2 bytes 6 cycles*
direct page indirect indexed by Y 31 2 bytes 5 cycles*
direct page indirect long indexed by Y 37 2 bytes 6 cycles*
Stack Relative 23 2 bytes 4 cycles*
stack relative indirect indexed by Y 33 2 bytes 7 cycles*
Flags Affected
N V M X D I Z C
. . . . . .

AND is a 65x instruction that performs a logical AND.

Cycle Penalties

See Also

External Links