FMULT (Super FX): Difference between revisions

Revision as of 02:47, 16 December 2023


Basic Info
Opcode	Length	ROM Speed	RAM Speed	Cache Speed
9F	1 byte	7 or 11 cycles	7 or 11 cycles	4 or 8 cycle


Flags Affected
B	ALT1	ALT2	O/V	S	CY	Z
0	0	0	.

FMULT is a Super FX instruction that performs a signed multiplication. The two factors are the source register and R₆. The upper 16 bits of the 32-bit product are stored in the destination register. Bit 15 of the product is stored in CY. The lower 15 bits of the product appear to be discarded.

The exact speed depends on the state of the CFGR register.

R₄ cannot serve as the destination register.

External Links

Official Nintendo documentation on FMULT: Page 2-9-46 of Book II
example: page 2-9-47, lbid.

@@ Line 35: / Line 35: @@
 |}
-'''FMULT''' is a [[Super FX]] instruction that performs a signed multiplication.  The two factors are the [[source register]] and R6.  The upper 16 bits of the 32-bit product are stored in the [[destination register]].  Bit 15 of the product is stored in [[CY]].  The lower 15 bits of the product appear to be discarded.
+'''FMULT''' is a [[Super FX]] instruction that performs a signed multiplication.  The two factors are the [[source register]] and R<sub>6</sub>.  The upper 16 bits of the 32-bit product are stored in the [[destination register]].  Bit 15 of the product is stored in [[CY]].  The lower 15 bits of the product appear to be discarded.
 The exact speed depends on the state of the [[CFGR]] register.
-R4 cannot serve as the destination register.
+R<sub>4</sub> cannot serve as the destination register.
 === See Also ===