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Program Bank Register: Difference between revisions
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The '''Program Bank Register''' (PBR) exists on the [[65c816]]. It is 8 bits wide. | The '''Program Bank Register''' (PBR) exists on the [[65c816]]. It is 8 bits wide. It is cleared to zero on reset.<sup>[2]</sup> | ||
There is also a program bank register on the [[GSU]].<sup>[1]</sup> | There is also a program bank register on the [[GSU]].<sup>[1]</sup> | ||
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=== Reference === | === Reference === | ||
# section 4.5 on [https://archive.org/details/SNESDevManual/book2/page/n111 page 2-4-5 of Book II] | # section 4.5 on [https://archive.org/details/SNESDevManual/book2/page/n111 page 2-4-5 of Book II] | ||
# section 2.9 on page 7 of 65c816 datasheet | |||
[[Category:SNES Hardware]] | [[Category:SNES Hardware]] | ||
[[Category:Registers]] | [[Category:Registers]] | ||
Revision as of 07:18, 19 December 2023
The Program Bank Register (PBR) exists on the 65c816. It is 8 bits wide. It is cleared to zero on reset.[2]
There is also a program bank register on the GSU.[1]
See Also
Reference
- section 4.5 on page 2-4-5 of Book II
- section 2.9 on page 7 of 65c816 datasheet