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Program Bank Register: Difference between revisions
From SnesLab
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# paragraph 4.5 on [https://archive.org/details/SNESDevManual/book2/page/n111 page 2-4-5 of Book II] | # paragraph 4.5 on [https://archive.org/details/SNESDevManual/book2/page/n111 page 2-4-5 of Book II] | ||
# section 2.9 on page 7 of 65c816 datasheet | # section 2.9 on page 7 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf | ||
[[Category:SNES Hardware]] | [[Category:SNES Hardware]] | ||
[[Category:Registers]] | [[Category:Registers]] | ||
Revision as of 23:22, 28 June 2024
The Program Bank Register (PBR) exists on the 65c816. It is 8 bits wide. It is cleared to zero on reset.[2]
There is also a program bank register on the GSU.[1]
See Also
Reference
- paragraph 4.5 on page 2-4-5 of Book II
- section 2.9 on page 7 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf