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Program Bank Register: Difference between revisions
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The '''Program Bank Register''' (PBR) exists on the [[65c816]]. It is 8 bits wide. It is cleared to zero on reset.<sup>[2]</sup> | The '''Program Bank Register''' (PBR) exists on the [[65c816]]. It is 8 bits wide. It is cleared to zero on reset.<sup>[2]</sup> [[PHK]] pushes it onto the [[stack]]. | ||
There is also a program bank register on the [[GSU]].<sup>[1]</sup> | There is also a program bank register on the [[GSU]].<sup>[1]</sup> | ||
=== See Also === | === See Also === | ||
* [[RTI]] | * [[RTI]] | ||
* [[Program Counter]] | * [[Program Counter]] | ||
Revision as of 23:23, 28 June 2024
The Program Bank Register (PBR) exists on the 65c816. It is 8 bits wide. It is cleared to zero on reset.[2] PHK pushes it onto the stack.
There is also a program bank register on the GSU.[1]
See Also
Reference
- paragraph 4.5 on page 2-4-5 of Book II
- section 2.9 on page 7 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf