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DIV2 (Super FX): Difference between revisions
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'''DIV2''' (DIVide by 2) is a [[Super FX]] instruction that shifts the value of the [[source register]]'s bits one place to the right while also leaving the most significant bit unchanged, storing the quotient in the [[destination register]]. The source register itself is left unchanged. Unlike [[ASR]], the output becomes zero if the input is 0xFFFF. | '''DIV2''' (DIVide by 2) is a [[Super FX]] instruction that shifts the value of the [[source register]]'s bits one place to the right while also leaving the most significant bit unchanged, storing the quotient in the [[destination register]]. The source register itself is left unchanged. Unlike [[ASR]], the output becomes zero if the input is 0xFFFF. | ||
The source and destination registers should be specified in advance using [[WITH]], [[FROM]], or [[TO]]. Otherwise, R<sub>0</sub> serves as the default. | |||
==== Syntax ==== | ==== Syntax ==== | ||
Revision as of 18:37, 9 July 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | ROM Speed | RAM Speed | Cache Speed | ||
| Implied (type 1) | 3D96 | 2 bytes | 6 cycles | 6 cycles | 2 cycles | ||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | . | |||||
DIV2 (DIVide by 2) is a Super FX instruction that shifts the value of the source register's bits one place to the right while also leaving the most significant bit unchanged, storing the quotient in the destination register. The source register itself is left unchanged. Unlike ASR, the output becomes zero if the input is 0xFFFF.
The source and destination registers should be specified in advance using WITH, FROM, or TO. Otherwise, R0 serves as the default.
Syntax
DIV2
Example
Let:
Sreg : R7 Dreg : R2 R7 = 4635h (0100 0110 0011 0101b) CY = 0
After executing DIV2:
R7 = 231Ah (0010 0011 0001 1010b) CY = 1
See Also
External Links
- Official Nintendo documentation on DIV2: 9.32 on page 2-9-44 of Book II
- example: page 2-9-45, lbid.