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CPX: Difference between revisions

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(→‎Syntax: 2 or 3 bytes for immediate data)
(→‎External Links: Clark link)
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* undisbeliever on CPX: https://undisbeliever.net/snesdev/65816-opcodes.html#cpx-compare-index-register-x-with-memory
* undisbeliever on CPX: https://undisbeliever.net/snesdev/65816-opcodes.html#cpx-compare-index-register-x-with-memory
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#CPX
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#CPX
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.1.1.2


[[Category:ASM]]
[[Category:ASM]]
[[Category:Group Three Instructions]]
[[Category:Group Three Instructions]]
[[Category:Inherited from 6502]]
[[Category:Inherited from 6502]]

Revision as of 01:11, 24 July 2024

Basic Info
Addressing Mode Opcode Length Speed
Immediate E0 2/3 bytes 2 cycles*
Absolute EC 3 bytes 4 cycles*
Direct Page E4 2 bytes 3 cycles*
Flags Affected
N V M X D I Z C
. . . . .

CPX (Compare X) is a 65x instruction that compares the value of the X index register to something. Internally, this is done via a subtraction, but the difference is not stored anywhere. Thus, the purpose of CPX is to setup the flags. The index register X is the minuend. Depending on the addressing mode used, the subtrahend will be either an immediate value or the value stored at the effective address specified by the operand. The contents at the effective address (when not using immediate data) and the X index register both remain unchanged.

CPX assumes its operands are unsigned.

Syntax

CPX #const
CPX addr
CPX dp

In immediate addressing, the 65c816 expects the number of bytes of immediate data to match the current size of the index registers.

Cycle Penalties

  • CPX takes an extra cycle in all three addressing modes when the index registers are 16 bits wide.
  • In direct page addressing only, CPX takes an extra cycle when the low byte of the direct register is nonzero.

See Also

External Links