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PLX: Difference between revisions
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==== Cycle Penalty ==== | |||
* PLX takes one additional cycle if the index registers are 16 bits wide. | * PLX takes one additional cycle if the index registers are 16 bits wide. | ||
Latest revision as of 17:39, 23 August 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | Speed | ||||
| Stack (Pull) | FA | 1 byte | 4 cycles* | ||||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| N | V | M | X | D | I | Z | C | |
| N | . | . | . | . | . | Z | . | |
PLX (PulL X) is a 65x instruction that pulls the value at the top of the stack into the X index register. PLX increments the stack pointer before the pull.
The Labiak textbook seems to have omitted the fact that according to the datasheet, PLX affects the zero flag.
Syntax
PLX
Cycle Penalty
- PLX takes one additional cycle if the index registers are 16 bits wide.
See Also
External Links
- Eyes & Lichty, page 487 on PLX
- Labiak, page 171 on PLX
- snes9x implementation of PLX: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2156