ORA

Basic Info
Addressing Mode	Opcode	Length	Speed
Immediate	09	2/3 bytes	2 cycles*
Absolute	0D	3 bytes	4 cycles*
Absolute Long	0F	4 bytes	5 cycles*
Direct Page	05	2 bytes	3 cycles*
Direct Page Indirect	12	2 bytes	5 cycles*
Direct Page Indirect Long	07	2 bytes	6 cycles*
Absolute Indexed by X	1D	3 bytes	4 cycles*
Absolute Long Indexed by X	1F	4 bytes	5 cycles*
Absolute Indexed by Y	19	3 bytes	4 cycles*
Direct Page Indexed by X	15	2 bytes	4 cycles*
Direct Page Indexed Indirect by X	01	2 bytes	6 cycles*
Direct Page Indirect Indexed by Y	11	2 bytes	5 cycles*
Direct Page Indirect Long Indexed by Y	17	2 bytes	6 cycles*
Stack Relative	03	2 bytes	4 cycles*
Stack Relative Indirect Indexed by Y	13	2 bytes	7 cycles*

Flags Affected
N	V	M	X	D	I	Z	C
N	.	.	.	.	.	Z	.

ORA is a 65x instruction that performs a logical OR between the datum at the effective address and the accumulator and stores the disjunction in the accumulator. The size of the accumulator determines whether 8 or 16 bits are ORed.

Syntax

ORA #const
ORA addr
ORA long
ORA dp
ORA (dp)
ORA [dp]
ORA addr, X
ORA long, X
ORA addr, Y
ORA dp, X
ORA (dp, X)
ORA (dp), Y
ORA [dp], Y
ORA sr, S
ORA (sr, S), Y

Cycle Penalties

• In all addressing modes, ORA takes one extra cycle when the accumulator is 16 bits wide.
• In direct page addressing modes, ORA takes another extra cycle if the low byte of the direct page register is nonzero.

See Also

• AND
• EOR
• OR (Super FX)
• XOR (Super FX)

External Links

• Eyes & Lichty, page 471 on ORA
• Labiak, page 156 on ORA
• 2.2.4.2 on MCS6500 Manual, page 21 on ORA
• Carr, page 266 on ORA
• Leventhal, page 3-79 on ORA
• snes9x implementation of ORA: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L917
• undisbeliever on ORA: https://undisbeliever.net/snesdev/65816-opcodes.html#ora-or-accumulator-with-memory
• Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#ORA
• Bruce, Clark. http://www.6502.org/tutorials/65c816opcodes.html#6.1.2.1