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Non-Maskable Interrupt: Difference between revisions
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=== References === | === References === | ||
* 7.19 Interrupt Priorities, page 53: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf | * 7.19 Interrupt Priorities, page 53: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf | ||
=== External Links === | |||
* snes9x implementation of NMI: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2663 | |||
Revision as of 20:26, 17 May 2023
A non-maskable interrupt (NMI) is an interrupt that cannot be ignored. The PPU normally generates an NMI at the beginning of the vertical blanking period, which is received by the Ricoh CPU.
NMIs have higher priority than IRQs, but lower priority than Reset.
References
- 7.19 Interrupt Priorities, page 53: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf
External Links
- snes9x implementation of NMI: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2663