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Non-Maskable Interrupt: Difference between revisions
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NMIs have higher priority than [[IRQ]]s, but lower priority than Reset. | NMIs have higher priority than [[IRQ]]s, but lower priority than Reset. | ||
=== See Also === | |||
* [[NMI Enable Flag]] | |||
=== References === | === References === | ||
Revision as of 06:20, 6 July 2023
A non-maskable interrupt (NMI) is an interrupt that cannot be ignored. The PPU normally generates an NMI at the beginning of the vertical blanking period, which is received by the Ricoh CPU.
NMIs have higher priority than IRQs, but lower priority than Reset.
See Also
References
- 7.19 Interrupt Priorities, page 53: https://www.westerndesigncenter.com/wdc/documentation/w65c816s.pdf
External Links
- snes9x implementation of NMI: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2663