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Instruction Controller: Difference between revisions
From SnesLab
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The '''Instruction Controller''' is one of the six components of the [[Super FX]]. | The '''Instruction Controller''' is one of the six components of the [[Super FX]]. | ||
It contains the cache pipeline decoder. It receives input from: | It contains the [[cache pipeline decoder]]. It receives input from: | ||
* the [[Game Pak RAM Controller]] | * the [[Game Pak RAM Controller]] | ||
* the [[Game Pak ROM Controller]] | * the [[Game Pak ROM Controller]] | ||
Revision as of 01:59, 1 December 2023
The Instruction Controller is one of the six components of the Super FX.
It contains the cache pipeline decoder. It receives input from:
- the Game Pak RAM Controller
- the Game Pak ROM Controller
- the SNES CPU Interface (which it also outputs to)
References
- Figure 2-2-1 "GSU Functional Block Diagram" on page 2-2-1 of the official Super Nintendo development manual