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LSR: Difference between revisions

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|4E
|4E
|3 bytes
|3 bytes
|6 cycles
|6 cycles*
|+
|+
|direct page
|direct page
|46
|46
|2 bytes
|2 bytes
|5 cycles
|5 cycles*
|+
|+
|absolute indexed X
|absolute indexed X
|5E
|5E
|3 bytes
|3 bytes
|7 cycles
|7 cycles*
|+
|+
|direct page indexed X
|direct page indexed X
|56
|56
|2 bytes
|2 bytes
|6 cycles
|6 cycles*
|}
|}


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'''LSR''' (Logical Shift Right) is a 65x instruction that shifts a value one bit to the right (division by two).  The most significant bit becomes a zero.  The least significant bit is shifted into the [[carry flag]].
'''LSR''' (Logical Shift Right) is a 65x instruction that shifts a value one bit to the right (division by two).  The most significant bit becomes a zero.  The least significant bit is shifted into the [[carry flag]].  In [[direct page addressing]] modes, LSR takes another extra cycle if the low byte of the [[direct page register]] is nonzero.


=== See Also ===
=== See Also ===

Revision as of 01:20, 20 November 2023

Basic Info
Addressing Mode Opcode Length Speed
accumulator 4A 1 byte 2 cycles
absolute 4E 3 bytes 6 cycles*
direct page 46 2 bytes 5 cycles*
absolute indexed X 5E 3 bytes 7 cycles*
direct page indexed X 56 2 bytes 6 cycles*
Flags Affected
N V M X D I Z C
0 . . . . .

LSR (Logical Shift Right) is a 65x instruction that shifts a value one bit to the right (division by two). The most significant bit becomes a zero. The least significant bit is shifted into the carry flag. In direct page addressing modes, LSR takes another extra cycle if the low byte of the direct page register is nonzero.

See Also

External Links

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