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PLP: Difference between revisions

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Revision as of 04:41, 24 November 2023

Basic Info
Addressing Mode Opcode Length Speed
Stack (Pull) 28 1 byte 4 cycles
Flags Affected
N V M X / B D I Z C
65c816 native mode
6502 emulation mode .

PLP (PulL status flags) is a 65x instruction that pulls the 8-bit value at the top of the stack into the status register.

See Also

External Links

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