We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS
Cache RAM: Difference between revisions
From SnesLab
(category address spaces) |
(→Reference: execution in cache ram) |
||
| Line 7: | Line 7: | ||
# [https://archive.org/details/SNESDevManual/book2/page/n131 page 2-6-9 of Book II] of the official Super Nintendo development manual | # [https://archive.org/details/SNESDevManual/book2/page/n131 page 2-6-9 of Book II] of the official Super Nintendo development manual | ||
# [https://archive.org/details/SNESDevManual/book2/page/n132 page 2-6-10 of Book II] of the official Super Nintendo development manual | # [https://archive.org/details/SNESDevManual/book2/page/n132 page 2-6-10 of Book II] of the official Super Nintendo development manual | ||
# Execution in Cache RAM. [https://archive.org/details/SNESDevManual/book2/page/n123 page 2-6-1 of Book II] of the official Super Nintendo development manual | |||
[[Category:SNES Hardware]] | [[Category:SNES Hardware]] | ||
[[Category:Address Spaces]] | [[Category:Address Spaces]] | ||
Revision as of 02:03, 29 November 2023
Cache RAM is a region of 512 bytes on the Super FX. Access to it is six times faster than Game Pak ROM or Game Pak RAM.1 It is divided into 32 blocks, each block being 16 bytes.2
See Also
Reference
- page 2-6-9 of Book II of the official Super Nintendo development manual
- page 2-6-10 of Book II of the official Super Nintendo development manual
- Execution in Cache RAM. page 2-6-1 of Book II of the official Super Nintendo development manual