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ADC (Super FX): Difference between revisions
From SnesLab
m (Fixed opcode for ADC Rn.) |
(2 byte Instructions) |
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[[Category:Super FX]] | [[Category:Super FX]] | ||
[[Category:Arithmetic Operation Instructions]] | [[Category:Arithmetic Operation Instructions]] | ||
[[Category:Two-byte Instructions]] |
Revision as of 17:34, 29 November 2023
Basic Info | |||||||
---|---|---|---|---|---|---|---|
Addressing Mode | Opcode | Length | ROM Speed | RAM Speed | Cache Speed | ||
3D5n | 2 bytes | 6 cycles | 6 cycles | 2 cycle | |||
Immediate | 3F5n | 2 bytes | 6 cycles | 6 cycles | 2 cycle |
Flags Affected | ||||||||
---|---|---|---|---|---|---|---|---|
B | ALT1 | ALT2 | O/V | S | CY | Z | ||
0 | 0 | 0 |
ADC (Add with carry) is a Super FX instruction that performs an addition. The source register is always the first addend. The second addend may be any of the 16 R registers or an immediate value. The third addend is CY. The sum is stored in the destination register.
See Also
External Links
- Official Nintendo documentation on ADC: Page 2-9-3 of Book II