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PLP: Difference between revisions

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* [[Labiak]] page 170 on PLP: https://archive.org/details/Programming_the_65816/page/n180
* [[Labiak]] page 170 on PLP: https://archive.org/details/Programming_the_65816/page/n180
* [[MCS6500 Manual]] page on PLP: https://archive.org/details/mos_microcomputers_programming_manual/page/n142
* [[MCS6500 Manual]] page on PLP: https://archive.org/details/mos_microcomputers_programming_manual/page/n142
* [[Carr]] page on PLP: https://archive.org/details/6502UsersManual/page/n281
* [[Carr]] page 268 on PLP: https://archive.org/details/6502UsersManual/page/n281
* [[Leventhal]] page 3-84 on PLP: https://archive.org/details/6502-assembly-language-programming/page/n133
* [[Leventhal]] page 3-84 on PLP: https://archive.org/details/6502-assembly-language-programming/page/n133
* snes9x implementation of PLP: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2099
* snes9x implementation of PLP: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2099

Revision as of 05:25, 5 December 2023

Basic Info
Addressing Mode Opcode Length Speed
Stack (Pull) 28 1 byte 4 cycles
Flags Affected
N V M X / B D I Z C
65c816 native mode
6502 emulation mode .

PLP (PulL status flags) is a 65x instruction that pulls the 8-bit value at the top of the stack into the status register.

See Also

External Links