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CLD: Difference between revisions

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[[Category:One-byte Instructions]]
[[Category:One-byte Instructions]]
[[Category:Implied Instructions]]
[[Category:Implied Instructions]]
[[Category:Two-cycle Instructions]]

Revision as of 11:43, 14 December 2023

Basic Info
Addressing Mode Opcode Length Speed
Implied (type 2) D8 1 byte 2 cycles
Flags Affected
N V M X D I Z C
. . . . 0 . . .

CLD is a 65x instruction that clears the decimal mode flag, switching the processor back into binary mode.

See Also

External Links