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ADC (Super FX): Difference between revisions

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(blurb about specifying sreg/dreg in advance)
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ADC #n
ADC #n
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</pre>
==== Example 1 ====
ADC  R<sub>1</sub>    ; R<sub>0</sub> + R<sub>1</sub> + CY -> R<sub>0</sub>
WITH  R<sub>2</sub>    ; set the source/destination regs to R<sub>2</sub>
ADC  R<sub>3</sub>    ; R<sub>2</sub> + R<sub>3</sub> + CY -> R<sub>2</sub>
ADC  R<sub>2</sub>    ; R<sub>0</sub> + R<sub>2</sub> + CY -> R<sub>0</sub>


=== See Also ===
=== See Also ===

Revision as of 19:32, 10 July 2024

Basic Info
Addressing Mode Opcode Length ROM Speed RAM Speed Cache Speed
Implied (type 1) 3D5n 2 bytes 6 cycles 6 cycles 2 cycles
Immediate 3F5n 2 bytes 6 cycles 6 cycles 2 cycles
Flags Affected
B ALT1 ALT2 O/V S CY Z
0 0 0

ADC (Add with carry) is a Super FX instruction that performs an addition. The source register is always the first addend. The second addend may be any of the 16 R registers or an immediate value. The third addend is CY. The sum is stored in the destination register.

The source and destination registers should be specified in advance using WITH, FROM, or TO. Otherwise, R0 serves as the default.

Syntax

ADC Rn
ADC #n

Example 1

ADC   R1    ; R0 + R1 + CY -> R0
WITH  R2    ; set the source/destination regs to R2
ADC   R3    ; R2 + R3 + CY -> R2
ADC   R2    ; R0 + R2 + CY -> R0

See Also

External Links