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MUL (SPC700): Difference between revisions

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# Official Super Nintendo development manual on MUL: Table C-13, [https://archive.org/details/SNESDevManual/book1/page/n233 Appendix C-8 of Book I]
# Official Super Nintendo development manual on MUL: Table C-13, [https://archive.org/details/SNESDevManual/book1/page/n233 Appendix C-8 of Book I]
# https://forums.nesdev.org/viewtopic.php?p=141221#p141221
# https://forums.nesdev.org/viewtopic.php?p=141221#p141221
# https://github.com/yupferris/TasmShiz/blob/master/spc700.txt#L510


[[Category:ASM]]
[[Category:ASM]]

Revision as of 21:54, 13 July 2024

Basic Info
Addressing Mode Opcode Length Speed
Implied (type 1) CF 1 byte 9 cycles
Flags Affected
N V P B H I Z C
. . . . . .

MUL is an SPC700 instruction that multiplies the value in the Y index register by the value in the accumulator and stores the product in YA. The high byte of the product is stored in Y and the low byte is stored in A.[2]

Syntax

MUL

See Also

External Links

  1. Official Super Nintendo development manual on MUL: Table C-13, Appendix C-8 of Book I
  2. https://forums.nesdev.org/viewtopic.php?p=141221#p141221
  3. https://github.com/yupferris/TasmShiz/blob/master/spc700.txt#L510