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PLP: Difference between revisions

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|+
|+
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|N
|[[Negative Flag|N]]
|V
|[[Overflow Flag|V]]
|M
|[[M Flag|M]]
|X / B
|[[X Flag|X]] / B
|D
|[[Decimal Flag|D]]
|I
|[[I Flag|I]]
|Z
|[[Zero Flag|Z]]
|C
|[[Carry Flag|C]]
|+
|+
|[[65c816 native mode]]
|[[65c816 native mode]]

Revision as of 23:49, 21 July 2024

Basic Info
Addressing Mode Opcode Length Speed
Stack (Pull) 28 1 byte 4 cycles
Flags Affected
N V M X / B D I Z C
65c816 native mode
6502 emulation mode .

PLP (PulL status flags) is a 65x instruction that pulls the 8-bit value at the top of the stack into the status register. The stack pointer is incremented before the byte is pulled.

Syntax

PLP

See Also

External Links