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CLD: Difference between revisions

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(→‎See Also: CLC, CLV)
(→‎External Links: Clark link)
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* [[Leventhal]] page 3-53 on CLD: https://archive.org/details/6502-assembly-language-programming/page/n102
* [[Leventhal]] page 3-53 on CLD: https://archive.org/details/6502-assembly-language-programming/page/n102
* snes9x implementation of CLD: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L1434
* snes9x implementation of CLD: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L1434
* Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#6.4.1


[[Category:ASM]]
[[Category:ASM]]

Revision as of 01:47, 24 July 2024

Basic Info
Addressing Mode Opcode Length Speed
Implied (type 2) D8 1 byte 2 cycles
Flags Affected
N V M X D I Z C
. . . . 0 . . .

CLD is a 65x instruction that clears the decimal mode flag, switching the processor back into binary mode so ADC and SBC will operate normally.

Syntax

CLD

See Also

External Links