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Program Bank Register: Difference between revisions
From SnesLab
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* [[JSL]] | * [[JSL]] | ||
* [[JMP]] absolute long | * [[JMP]] absolute long | ||
Incrementing the [[program counter]] past FFFFh does not affect PBR.<sup>[4]</sup> | |||
There is also a program bank register on the [[GSU]].<sup>[1]</sup> It can be used to specify any mapped bank address.<sup>[3]</sup> | There is also a program bank register on the [[GSU]].<sup>[1]</sup> It can be used to specify any mapped bank address.<sup>[3]</sup> | ||
=== See Also === | === See Also === | ||
* [[Data Bank Register]] | * [[Data Bank Register]] | ||
* [[LJMP]] | * [[LJMP]] | ||
Revision as of 23:47, 31 July 2024
The Program Bank Register (PBR or K) exists on the 65c816. It tells the processor which bank to fetch the next opcode from. It is 8 bits wide. It is cleared to zero on reset.[2] PHK pushes it onto the stack, but there is no PLK to pull it.
PBR is affected only by:[4]
Incrementing the program counter past FFFFh does not affect PBR.[4]
There is also a program bank register on the GSU.[1] It can be used to specify any mapped bank address.[3]
See Also
References
- paragraph 4.5 on page 2-4-5 of Book II
- section 2.9 on page 7 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf
- Figure 2-3-2 Super FX Memory Map on page 2-3-4 of Book II
- section 3.4 Program Address Space of 65c816 datasheet