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COP: Difference between revisions
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COP triggers a software interrupt and control is routed to the COP handler, whose address is stored in the COP vector at $FFF4. | COP triggers a software interrupt and control is routed to the COP handler, whose address is stored in the COP vector at $FFF4. | ||
The PBR is cleared, but in native mode its previous value is pushed to the stack. | The [[PBR]] is cleared, but in native mode its previous value is pushed to the [[stack]]. | ||
==== Syntax ==== | ==== Syntax ==== | ||
Revision as of 23:03, 3 August 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | Speed | ||||
| Stack (Interrupt) | 02 | 2 bytes | 8 cycles* | ||||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| N | V | M | X | D | I | Z | C | |
| . | . | . | . | 0 | 1 | . | . | |
COP (Co-Processor) is a 65c816 instruction designed to run a co-processor command. The byte following the opcode is called the Signature Byte and is required by assemblers. Signature bytes of 80h to FFh are reserved by the Western Design Center. The state of the interrupt disable flag has no effect on the behavior of COP.
COP triggers a software interrupt and control is routed to the COP handler, whose address is stored in the COP vector at $FFF4.
The PBR is cleared, but in native mode its previous value is pushed to the stack.
Syntax
COP sig
Cycle Skipped
- COP takes one fewer cycle in emulation mode as it doesn't need to push the program counter bank register to the stack.
See Also
External Links
- Eyes & Lichty page 447, on COP: https://archive.org/details/0893037893ProgrammingThe65816/page/447
- Labiak page 135 on COP: https://archive.org/details/Programming_the_65816/page/n145
- snes9x implementation of COP: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L2738
- https://ersanio.gitbook.io/assembly-for-the-snes/deep-dives/misc
- https://undisbeliever.net/snesdev/65816-opcodes.html#software-interrupts