We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS
Program Bank Register: Difference between revisions
From SnesLab
(incrementing pc does not affect it) |
(→References: linkify GSU memory map) |
||
| Line 20: | Line 20: | ||
# paragraph 4.5 on [https://archive.org/details/SNESDevManual/book2/page/n111 page 2-4-5 of Book II] | # paragraph 4.5 on [https://archive.org/details/SNESDevManual/book2/page/n111 page 2-4-5 of Book II] | ||
# section 2.9 on page 7 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf | # section 2.9 on page 7 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf | ||
# Figure 2-3-2 Super FX Memory Map on page 2-3-4 of Book II | # Figure 2-3-2 Super FX Memory Map on [https://archive.org/details/SNESDevManual/book2/page/n106 page 2-3-4 of Book II] | ||
# section 3.4 Program Address Space of 65c816 datasheet | # section 3.4 Program Address Space of 65c816 datasheet | ||
[[Category:SNES Hardware]] | [[Category:SNES Hardware]] | ||
[[Category:Registers]] | [[Category:Registers]] | ||
Revision as of 20:38, 10 August 2024
The Program Bank Register (PBR or K) exists on the 65c816. It tells the processor which bank to fetch the next opcode from. It is 8 bits wide. It is cleared to zero on reset.[2] PHK pushes it onto the stack, but there is no PLK to pull it.
PBR is affected only by:[4]
Incrementing the program counter past FFFFh does not affect PBR.[4]
There is also a program bank register on the GSU.[1] It can be used to specify any mapped bank address.[3]
See Also
References
- paragraph 4.5 on page 2-4-5 of Book II
- section 2.9 on page 7 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf
- Figure 2-3-2 Super FX Memory Map on page 2-3-4 of Book II
- section 3.4 Program Address Space of 65c816 datasheet