We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS
DIV2 (Super FX): Difference between revisions
From SnesLab
(Added links to other bitshift operators, explanation to most significant bit and differenciation to ASR.) |
(added basic info) |
||
| Line 1: | Line 1: | ||
'''DIV2''' (DIVide by 2) is a [[Super FX]] instruction that shifts a register's bits one place to the right while also leaving the most significant bit unchanged. Unlike [[ASR]], the output becomes zero if the input is 0xFFFF. | '''DIV2''' (DIVide by 2) is a [[Super FX]] instruction that shifts a register's bits one place to the right while also leaving the most significant bit unchanged. Unlike [[ASR]], the output becomes zero if the input is 0xFFFF. | ||
{| class="wikitable" style="float:right;clear:right;width:40%" | |||
!colspan="8"|Basic Info | |||
|+ | |||
|'''Opcode''' | |||
|'''Length''' | |||
|'''ROM Speed''' | |||
|'''RAM Speed''' | |||
|'''Cache Speed''' | |||
|+ | |||
|3D96 | |||
|2 bytes | |||
|6 cycles | |||
|6 cycles | |||
|2 cycle | |||
|} | |||
{| class="wikitable" style="float:right;clear:right;width:30%" | {| class="wikitable" style="float:right;clear:right;width:30%" | ||
| Line 27: | Line 43: | ||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category: | [[Category:Super FX]] | ||
Revision as of 21:59, 5 May 2023
DIV2 (DIVide by 2) is a Super FX instruction that shifts a register's bits one place to the right while also leaving the most significant bit unchanged. Unlike ASR, the output becomes zero if the input is 0xFFFF.
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Opcode | Length | ROM Speed | RAM Speed | Cache Speed | |||
| 3D96 | 2 bytes | 6 cycles | 6 cycles | 2 cycle | |||
| Flags Clobbered | ||||||||
|---|---|---|---|---|---|---|---|---|
| B | ALT1 | ALT2 | O/V | S | CY | Z | ||
| 0 | 0 | 0 | . | |||||