AND: Difference between revisions

Revision as of 04:01, 18 May 2023

AND is a 65x instruction that performs a logical AND.


Basic Info
Addressing Mode	Opcode	Length	Speed
immediate	29	2 bytes	2 cycles
absolute	2D	3 bytes	4 cycles
absolute long	2F	4 bytes	5 cycles
direct page	25	2 bytes	3 cycles
direct page indirect	32	2 bytes	5 cycles
direct page indirect long	27	2 bytes	6 cycles
absolute indexed by X	3D	3 bytes	4 cycles
absolute long indexed by X	3F	4 bytes	5 cycles
absolute indexed by Y	39	3 bytes	4 cycles
direct page indexed by X	35	2 bytes	4 cycles
direct page indirect indexed by X	21	2 bytes	6 cycles
direct page indirect indexed by Y	31	2 bytes	5 cycles
direct page indirect long indexed by Y	37	2 bytes	6 cycles
stack relative	23	2 bytes	4 cycles
stack relative indirect indexed by Y	33	2 bytes	7 cycles


Flags Clobbered
N	V	M	X	D	I	Z	C
	.	.	.	.	.		.

@@ Line 117: / Line 117: @@
 * [[Carr]] page on AND: https://archive.org/details/6502UsersManual/page/n259
 * [[Leventhal]] page on AND: https://archive.org/details/6502-assembly-language-programming/page/n87
+* undisbeliever on AND: https://undisbeliever.net/snesdev/65816-opcodes.html#and-and-accumulator-with-memory
 [[Category:ASM]]
 [[Category:Group One Instructions]]
 [[Category:Inherited from 6502]]