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External Latch: Difference between revisions
From SnesLab
(alternate name of trace) |
(external latch flag note) |
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According to [[fullsnes]], it is the lightpen signal. | According to [[fullsnes]], it is the lightpen signal. | ||
There is also the external latch flag, which is bit 6 of 213Fh. | |||
[[Category:SNES Hardware]] | [[Category:SNES Hardware]] | ||
[[Category:Traces]] | [[Category:Traces]] | ||
Revision as of 10:13, 23 May 2023
The EXTLATCH line connects pin 29 of the S-PPU2 to JPIO7 on the Front Panel Daughterboard, where it is called JPIO7.
According to fullsnes, it is the lightpen signal.
There is also the external latch flag, which is bit 6 of 213Fh.